A highly regular multi-phase reseeding technique for scan-based BIST
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Delay Defect Characteristics and Testing Strategies
IEEE Design & Test
Embedded Deterministic Test for Low-Cost Manufacturing
IEEE Design & Test
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients
Journal of Electronic Testing: Theory and Applications
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
An Arithmetic Structure for Test Data Horizontal Compression
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
Planar High Performance Ring Generators
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
Matrix-based software test data decompression for systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A unified method for phase shifter computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
High Performance Dense Ring Generators
IEEE Transactions on Computers
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient unknown blocking using LFSR reseeding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Test response compactor with programmable selector
Proceedings of the 43rd annual Design Automation Conference
Scan-BIST based on cluster analysis and the encoding of repeating sequences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis of irregular combinational functions with large don't care sets
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Unknown blocking scheme for low control data volume and high observability
Proceedings of the conference on Design, automation and test in Europe
Test generation in the presence of timing exceptions and constraints
Proceedings of the 44th annual Design Automation Conference
Scan Test Response Compaction Combined with Diagnosis Capabilities
Journal of Electronic Testing: Theory and Applications
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
IEICE - Transactions on Information and Systems
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
X-tolerant Test Data Compaction with Accelerated Shift Registers
Journal of Electronic Testing: Theory and Applications
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On test generation with test vector improvement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
Journal of Electronic Testing: Theory and Applications
Masking of X-Values by Use of a Hierarchically Configurable Register
Journal of Electronic Testing: Theory and Applications
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Generation of mixed test sets for transition faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing two-pattern test cubes for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper introduces Embedded Deterministic Test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.