HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Test Resource Partitioning for SOCs
IEEE Design & Test
A Serial-Scan Test-Vector-Compression Methodology
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test Compaction in a Parallel Access Scan Environment
ATS '97 Proceedings of the 6th Asian Test Symposium
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Virtual Compression through Test Vector Stitching for Scan Based Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Reseeding-Based Test Set Embedding with Reduced Test Sequences
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A Huffman-based coding with efficient test application
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
A Variable-Length Coding Adjustable for Compressed Test Application
IEICE - Transactions on Information and Systems
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan power reduction in linear test data compression scheme
Proceedings of the 2009 International Conference on Computer-Aided Design
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architecture of the existing SCC scheme, while it attempts to overlap consecutive test vector seeds, thus providing increased flexibility in exploiting effectively the large volume of don't-care bits in test vectors. We also introduce modified ATPG algorithms upon the previous SCC scheme and explore various implementation strategies. Experimental data exhibit significant reductions on test time and volume over all current test compression techniques.