Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A scan BIST generation method using a markov source and partial bit-fixing
Proceedings of the 40th annual Design Automation Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
OPMISR: The Foundation for Compressed ATPG Vectors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On test data volume reduction for multiple scan chain designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
An Arithmetic Structure for Test Data Horizontal Compression
Proceedings of the conference on Design, automation and test in Europe - Volume 1
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Fast and energy-frugal deterministic test through efficient compression and compaction techniques
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Virtual Compression through Test Vector Stitching for Scan Based Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low cost scan test by test correlation utilization
Journal of Computer Science and Technology
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel design-for-test (DFT) technique is presented for designing a core with a 驴virtual scan chain驴 which looks (to the system integrator) like it is shorter than the real scan chain inside the core. The I/O pins of a core with a virtual scan chain are identical to the I/O pins of a core with a normal scan chain. For the system integrator, testing a core with a virtual scan chain is identical to testing a core with a normal scan chain. The only difference is that the virtual scan chain is much shorter so the size of the scan vectors and output response is smaller resulting in less test data and fewer scan shift cycles. The process of mapping the virtual scan vectors to real scan vectors is handled inside the core and is completely transparent to the system integrator. Using LFSRs to 驴expand驴 the shorter virtual test vector into a full test vector does it. Results indicate that virtual scan chains can be designed which are several times shorter than the real scan chains inside the core.