Zero-aliasing space compaction of test responses using multiple parity signatures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Reduced Scan Shift: A New Testing Method for Sequential Circuit
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Optimal Sequencing of Scan Registers
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Test-Clock Reduction Method for Scan-Designed Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
ATS '98 Proceedings of the 7th Asian Test Symposium
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
An Efficient Scan Tree Design for Test Time Reduction
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Test cost reduction for logic circuits: Reduction of test data volume and test application time
Systems and Computers in Japan
Segmented Addressable Scan Architecture
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
An Efficient Scan Tree Design for Compact Test Pattern Set
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Low cost scan test by test correlation utilization
Journal of Computer Science and Technology
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parity-scan design to reduce the cost of test application
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reconfiguration techniques for a single scan chain
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new scan approach is described, named 'Virtual Chain Partition' (VCP) architecture, capable of substantially reducing the test application time, test data volume and test power. The VCP architecture maintains the original scan cell order. A simple procedure is proposed, which uses the scan test set generated for the original circuit to determine the maximum reduction in test cycles obtainable with the architecture and to select the most suitable configuration for each circuit. The experiments carried out with the ISCAS 89 benchmarks show that the VCP architecture allows considerable reductions to be achieved both for single and multiple scan chain circuits.