Segmented Addressable Scan Architecture

Authors:
Ahmad Al-Yamani;Erik Chmelar;Mikhail Grinchuck
Affiliations:
LSI Logic Corporation;LSI Logic Corporation;LSI Logic Corporation
Venue:
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Year:
2005

Citing 0
Cited 3

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System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

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Abstract

This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.