Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A dynamic programming approach to the test point insertion problem
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A General Constructive Approach to Fault-Tolerant Design Using Redundancy
IEEE Transactions on Computers
Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A method for generating weighted random test pattern
IBM Journal of Research and Development
Large-area fault clusters and fault tolerance in VLSI circuits
IBM Journal of Research and Development
Fault Tolerance in VLSI Circuits
Computer
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
A variable observation time method for testing delay faults
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ATPG based on a novel grid-addressable latch element
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
PATRIOT—a boundary-scan test and diagnosis system
COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Reliability of majority voting based VLSI fault-tolerant circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Field-programmable gate arrays: reconfigurable logic for rapid prototyping and implementation of digital systems
Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Pseudo-random testing and signature analysis for mixed-signal circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Fault-tolerant computer system design
Fault-tolerant computer system design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Signals & systems (2nd ed.)
Testable path delay fault cover for sequential circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Digital systems design and prototyping using field programmable logic
Digital systems design and prototyping using field programmable logic
ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
RF microelectronics
A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reliable computer systems (3rd ed.): design and evaluation
Reliable computer systems (3rd ed.): design and evaluation
Digital systems engineering
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
IDDT Testing versus IDDQ Testing
Journal of Electronic Testing: Theory and Applications
Efficient test-point selection for scan-based BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Illegal state space identification for sequential circuit test generation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multiple error diagnosis based on xlists
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Estimation for maximum instantaneous current through supply lines for CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Spectrum
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A fault simulation methodology for MEMS
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Low Power BIST by Filtering Non-Detecting Vectors
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Line coverage of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Implementation of a linear histogram BIST for ADCs
Proceedings of the conference on Design, automation and test in Europe
Test generation based diagnosis of device parameters for analog circuits
Proceedings of the conference on Design, automation and test in Europe
A sigma-delta modulation based BIST scheme for mixed-signal circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BIST-based test and diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Improving bus test via IDDT and boundary scan
Proceedings of the 38th annual Design Automation Conference
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Vector generation for power supply noise estimation and verification of deep submicron designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic performance setting for dynamic voltage scaling
Proceedings of the 7th annual international conference on Mobile computing and networking
ED4I: Error Detection by Diverse Data and Duplicated Instructions
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Software-based diagnosis for processors
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
Design for Test: For Digital Integrated Circuits
Design for Test: For Digital Integrated Circuits
RF and Microwave Circuit Design for Wireless Communications
RF and Microwave Circuit Design for Wireless Communications
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Computer Networks
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Detailed design and evaluation of redundant multithreading alternatives
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Test Bus Sizing for System-on-a-Chip
IEEE Transactions on Computers
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
A Design Diversity Metric and Analysis of Redundant Systems
IEEE Transactions on Computers
Shift Register Sequences
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Generation of Electrically Induced Stimuli for MEMS Self-Test
Journal of Electronic Testing: Theory and Applications
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Wafer-Level Testing with a Membrane Probe
IEEE Design & Test
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Microprocessor IDDQ Testing: A Case Study
IEEE Design & Test
Analog Testing with Time Response Parameters
IEEE Design & Test
DC Built-In Self-Test for Linear Analog Circuits
IEEE Design & Test
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
FPGA Architectural Research: A Survey
IEEE Design & Test
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Effective Built-In Self-Test for Booth Multipliers
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
Poirot: Applications of a Logic Fault Diagnosis Tool
IEEE Design & Test
Using Electrical Bitmap Results from Embedded Memory to Enhance Yield
IEEE Design & Test
A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
IEEE Design & Test
Jitter Testing for Gigabit Serial Communication Transceivers
IEEE Design & Test
Online Testing Approach for Very Deep-Submicron ICs
IEEE Design & Test
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
The Road Ahead: The significance of packaging
IEEE Design & Test
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
IEEE Transactions on Computers
Multiple Fault Detection in Parity Checkers
IEEE Transactions on Computers
Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Instruction-Based Self-Testing of Processor Cores
Journal of Electronic Testing: Theory and Applications
RF MEMS: Theory, Design, and Technology
RF MEMS: Theory, Design, and Technology
A Signature Analyzer for Analog and Mixed-signal Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Neighbor selection for variance reduction in I_DDQ and other parametric data
Proceedings of the IEEE International Test Conference 2001
A case study on the implementation of the Illinois Scan Architecture
Proceedings of the IEEE International Test Conference 2001
Tailoring ATPG for embedded testing
Proceedings of the IEEE International Test Conference 2001
Testing gigabit multilane SerDes interfaces with passive jitter injection filters
Proceedings of the IEEE International Test Conference 2001
IS-FPGA: a new symmetric FPGA architecture with implicit scan
Proceedings of the IEEE International Test Conference 2001
Proceedings of the IEEE International Test Conference 2001
A Bulti-in Self-Test Strategy for Wireless Communication Systems
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Generation for Global Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
DFT Strategy for Intel Microprocessors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proposal to Simplify Development of a Mixed-Signal Test Standard
Proceedings of the IEEE International Test Conference on Test and Design Validity
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Mixed-Mode BIST Using Embedded Processors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study
Proceedings of the IEEE International Test Conference
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Proceedings of the IEEE International Test Conference
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Testing the 400-MHz IBM Generation-4 CMOS Chip
Proceedings of the IEEE International Test Conference
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
IEEE P1149.4-Almost a Standard
Proceedings of the IEEE International Test Conference
Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams
Proceedings of the IEEE International Test Conference
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
Development of a MEMS Testing Methodology
Proceedings of the IEEE International Test Conference
Pentium® Pro Processor Design for Test and Debug
Proceedings of the IEEE International Test Conference
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis and characterization of timing-related defects by time-dependent light emission
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Skewed-Load Transition Test: Part 2, Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A method of serial data jitter analysis using one-shot time interval measurements
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Quality and Single-Stuck Faults
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Failure modes for stiction in surface-micromachined MEMS
ITC '98 Proceedings of the 1998 IEEE International Test Conference
MEMS fault model generation using CARAMEL
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Core test connectivity, communication, and control
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Novel optical probing technique for flip chip packaged microprocessors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
Two-dimensional test data compression for scan-based deterministic BIST
Proceedings of the IEEE International Test Conference 2001
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Testing interconnects for noise and skew in gigahertz SoCs
Proceedings of the IEEE International Test Conference 2001
A building block BIST methodology for SOC designs: a case study
Proceedings of the IEEE International Test Conference 2001
A token scan architecture for low power testing
Proceedings of the IEEE International Test Conference 2001
Multiple-output propagation transition fault test
Proceedings of the IEEE International Test Conference 2001
FedEx - a fast bridging fault extractor
Proceedings of the IEEE International Test Conference 2001
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Proceedings of the 40th annual Design Automation Conference
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
ATS '99 Proceedings of the 8th Asian Test Symposium
Peak-power reduction for multiple-scan circuits during test application
ATS '00 Proceedings of the 9th Asian Test Symposium
Testing Embedded Memories: Is BIST the Ultimate Solution?
ATS '98 Proceedings of the 7th Asian Test Symposium
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
ATS '02 Proceedings of the 11th Asian Test Symposium
Iddq Testing for High Performance CMOS - The Next Ten Years
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A New BIST Architecture for Low Power Circuits
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Towards an ADC BIST Scheme Using the Histogram Test Technique
ETW '00 Proceedings of the IEEE European Test Workshop
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Design rule checking and analysis of IC mask designs
DAC '76 Proceedings of the 13th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Quantitative analysis of very-low-voltage testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Power Dissipation During Testing: Should We Worry About it?
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Introduction to RF Testing: Device, Method and System
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Defect-Oriented Test Scheduling
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Power/Energy BIST Scheme for Datapaths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Delta Iddq for Testing Reliability
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
BIST-Aided Scan Test - A New Method for Test Cost Reduction
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Efficient Seed Utilization for Reseeding based Compression
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Testable Design and Testing of Micro-Electro-Fluidic Arrays
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Power Constrained Test Scheduling with Dynamically Varied TAM
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
The Impact of NoC Reuse on the Testing of Core-based Systems
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Analysis of Failure Sources in Surface-Micromachined MEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Empirical Study on the Effects of Test Type Ordering on
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimization Trade-offs for Vector Volume and Test Power
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Driven Chaining of Flip-Flops in Scan Architectures
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On the Use of k-tuples for SoC Test Schedule Representation
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Architecting Millisecond Test Solutions for Wireless Phone RFIC's
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Parametric Failures in CMOS ICs " A Defect-Based Analysis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Re-Using DFT Logic for Functional and Silicon Debugging Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Scalable,Low Cost Design-for-Test Architecture for UltraSPARC" Chip Multi-Processors
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Screening MinVDD Outliers Using Feed-Forward Voltage Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Built-In Self Test of CMOS-MEMS Accelerometers
ITC '02 Proceedings of the 2002 IEEE International Test Conference
BIST-Based Diagnosis of FPGA Interconnect
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On Structural vs. Functional Testing for Delay Faults
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Evaluation of Early Failure Screening Methods
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
The Effectiveness of IDDQ and High Voltage Stress for Burn-in Elimination
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
Test Scheduling and Scan-Chain Division under Power Constraint
ATS '01 Proceedings of the 10th Asian Test Symposium
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Hybrid BIST Using Partially Rotational Scan
ATS '01 Proceedings of the 10th Asian Test Symposium
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits
ATS '01 Proceedings of the 10th Asian Test Symposium
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
ATS '01 Proceedings of the 10th Asian Test Symposium
Yield Increase of VLSI after Redundancy-Repairing
ATS '01 Proceedings of the 10th Asian Test Symposium
A Signature Test Framework for Rapid Production Testing of RF Circuits
Proceedings of the conference on Design, automation and test in Europe
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Transformed pseudo-random patterns for BIST
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Electrically Induced Stimuli For MEMS Self-Test
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Diagnosis of Sequence-Dependent Chips
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Economics for Multi-site Test with Modern Cost Reduction Techniques
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
BIST-Based Delay-Fault Testing in FPGAs
Journal of Electronic Testing: Theory and Applications
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A New Method for Jitter Decomposition Through Its Distribution Tail Fitting
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Applying Defect-Based Test to Embedded Memories in a COT Model
MTDT '03 Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing
Testing of Digital Systems
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
IEEE Design & Test
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
ETW '03 Proceedings of the 8th IEEE European Test Workshop
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A circuit level fault model for resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Paradigm Shift For Jitter and Noise In Design and Test GB/s Communication Systems
ICCD '03 Proceedings of the 21st International Conference on Computer Design
ICCD '03 Proceedings of the 21st International Conference on Computer Design
IEEE Transactions on Computers
Hybrid BIST Using an Incrementally Guided LFSR
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
BiST Model for IC RF-Transceiver Front-End
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Constrained ATPG for Broadside Transition Testing
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
CodSim—A Combined Delay Fault Simulator
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computers
Concurrent RF Test Using Optimized Modulated RF Stimuli
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Random Access Scan: A solution to test power, test data volume and test time
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
On-chip testing of embedded transducers
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Wrapper Design for Testing IP Cores with Multiple Clock Domains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Synthesis for Manufacturability: A Sanity Check
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Power Supply Noise Monitor for Signal Integrity Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
CMOS Electronics: How It Works, How It Fails
CMOS Electronics: How It Works, How It Fails
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Modal Built-In Self-Test for Symmetric Microsystems
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Defects and Faults in Quantum Cellular Automata at Nano Scale
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Defect-Aware SOC Test Scheduling
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Production Testing of Rf and System-On-A-Chip Devices for Wireless Communications (Artech House Microwave Library)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Efficient on-line testing of FPGAs with provable diagnosabilities
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
IEEE Design & Test
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz
IEEE Design & Test
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RF-BIST: Loopback Spectral Signature Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Mixed Loopback BiST for RF Digital Transceivers
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Commercial Fault Tolerance: A Tale of Two Systems
IEEE Transactions on Dependable and Secure Computing
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low Power Test Data Compression Based on LFSR Reseeding
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Intelligible Test Techniques to Support Error-Tolerance
ATS '04 Proceedings of the 13th Asian Test Symposium
Microarchitecture and Design Challenges for Gigascale Integration
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Rapid Generation of Thermal-Safe Test Schedules
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Stochastic Power Grid Analysis Considering Process Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
RF MEMS in wireless architectures
Proceedings of the 42nd annual Design Automation Conference
Variations-aware low-power design with voltage scaling
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
An effective DFM strategy requires accurate process and IP pre-characterization
Proceedings of the 42nd annual Design Automation Conference
Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Effective TARO Pattern Generation
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Low-Cost Alternate EVM Test for Wireless Receiver Systems
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOS
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Segmented Addressable Scan Architecture
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Do We Need Anything More Than Single Bit Error Correction (ECC)?
MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Process Variation Tolerant Online Current Monitor for Robust Systems
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
At-Speed Logic BIST Architecture for Multi-Clock Designs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Hardware Ef.cient LBISTWith Complementary Weights
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Defects, Yield, and Design in Sublithographic Nano-electronics
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Design and Analysis of Self-Repairable MEMS Accelerometer
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Novel Transition Fault ATPG That Reduces Yield Loss
IEEE Design & Test
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Low-cost Production Test of BER for Wireless Receivers
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Bridge Defect Diagnosis with Physical Information
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The care and feeding of your statistical static timer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Test Cost Reduction Using Partitioned Grid Random Access Scan
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Low-Cost Production Testing of Wireless Transmitters
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
An Automated, Complete, Structural Test Solution for SERDES
ITC '04 Proceedings of the International Test Conference on International Test Conference
MRAM Defect Analysis and Fault Modeli
ITC '04 Proceedings of the International Test Conference on International Test Conference
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
AUTOMATIC LINEARITY (IP3) TEST WITH BUILT-IN PATTERN GENERATOR AND ANALYZER
ITC '04 Proceedings of the International Test Conference on International Test Conference
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Application-Dependent Diagnosis of FPGAs
ITC '04 Proceedings of the International Test Conference on International Test Conference
Trends in manufacturing test methods and their implications
ITC '04 Proceedings of the International Test Conference on International Test Conference
Tester Architecture For The Source Synchronous Bus
ITC '04 Proceedings of the International Test Conference on International Test Conference
Use of Embedded Sensors for Built-In-Test of RF Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays
ITC '04 Proceedings of the International Test Conference on International Test Conference
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics
ITC '04 Proceedings of the International Test Conference on International Test Conference
Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications
ITC '04 Proceedings of the International Test Conference on International Test Conference
THE LEADING EDGE OF PRODUCTION WAFER PROBE TEST TECHNOLOGY
ITC '04 Proceedings of the International Test Conference on International Test Conference
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores
ITC '04 Proceedings of the International Test Conference on International Test Conference
Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE
ITC '04 Proceedings of the International Test Conference on International Test Conference
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints
ITC '04 Proceedings of the International Test Conference on International Test Conference
Elimination of Traditional Functional Testing of Interface Timings at Intel
ITC '04 Proceedings of the International Test Conference on International Test Conference
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Propagation delay fault: a new fault model to test delay faults
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Evaluation of the statistical delay quality model
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
DFM Metrics for Standard Cells
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Device and Technology Challenges for Nanoscale CMOS
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
PRDC '05 Proceedings of the 11th Pacific Rim International Symposium on Dependable Computing
BIST for Network-on-Chip Interconnect Infrastructures
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Interconnect Testing for Networks on Chips
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
SCT: An Approach For Testing and Configuring Nanoscale Devices
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Networks on chips for high-end consumer-electronics TV system architectures
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Test generation for combinational quantum cellular automata (QCA) circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Pseudorandom functional BIST for linear and nonlinear MEMS
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Minimizing test power in SRAM through reduction of pre-charge activity
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Dynamic Voltage Scaling Aware Delay Fault Testing
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
System-in-Package Testing: Problems and Solutions
IEEE Design & Test
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Systematic software-based self-test for pipelined processors
Proceedings of the 43rd annual Design Automation Conference
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Computer Science and Technology
Survey of Test Vector Compression Techniques
IEEE Design & Test
Application-independent defect tolerance of reconfigurable nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Reliability Analysis of Self-Repairable MEMS Accelerometer
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
ATS '06 Proceedings of the 15th Asian Test Symposium
Test Data Compression Based on Clustered Random Access Scan
ATS '06 Proceedings of the 15th Asian Test Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing)
Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing)
Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library)
Integrated Circuit Design for High-Speed Frequency Synthesis (Artech House Microwave Library)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Built-in-self-test techniques for MEMS
Microelectronics Journal
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Testing Microelectronic Biofluidic Systems
IEEE Design & Test
Electronic test solutions for FlowFET fluidic arrays
DTIP '03 Proceedings of the Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS
Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips
ETS '07 Proceedings of the 12th IEEE European Test Symposium
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Testable design for advanced serial-link transceivers
Proceedings of the conference on Design, automation and test in Europe
A two-tone test method for continuous-time adaptive equalizers
Proceedings of the conference on Design, automation and test in Europe
Automated design of misaligned-carbon-nanotube-immune circuits
Proceedings of the 44th annual Design Automation Conference
IEEE Design & Test
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
A New Design Method for m-Out-of-n TSC Checkers
IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code
IEEE Transactions on Computers
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Functional Testing of Microprocessors
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
A Highly Efficient Redundancy Scheme: Self-Purging Redundancy
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
An Algebraic Model of Fault-Masking Logic Circuits
IEEE Transactions on Computers
A Class of Test Generators for Built-In Testing
IEEE Transactions on Computers
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra-wideband communications: fundamentals and applications
Ultra-wideband communications: fundamentals and applications
Seamless Test of Digital Components in Mixed-Signal Paths
IEEE Design & Test
IEEE Design & Test
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A statistical approach to the design of diffused junction transistors
IBM Journal of Research and Development
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
IBM S/390 parallel enterprise server G5 fault tolerance: a historical perspective
IBM Journal of Research and Development
Redundancy management technique for space shuttle computers
IBM Journal of Research and Development
Micromechanical membrane switches on silicon
IBM Journal of Research and Development
Beyond the conventional transistor
IBM Journal of Research and Development
microSPARCTM: a case-study of scan based debug
ITC'94 Proceedings of the 1994 international conference on Test
ATPG for heat dissipation minimization during test application
ITC'94 Proceedings of the 1994 international conference on Test
Defect classes - an overdue paradigm for CMOS IC testing
ITC'94 Proceedings of the 1994 international conference on Test
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
IC quality and test transparency
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Statistical delay fault coverage and defect level for delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the detection of delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 1: concepts and coverage metrics
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Design of test pattern generators for built-in test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Automatic linearity and frequency response tests with built-in pattern generator and analyzer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated testability enhancements for logic brick libraries
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A robust pulsed flip-flop and its use in enhanced scan design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
DFT and minimum leakage pattern generation for static power reduction during test and burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test exploration and validation using transaction level models
Proceedings of the Conference on Design, Automation and Test in Europe
Evolutionary design of reconfiguration strategies to reduce the test application time
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Exploration of FPGA interconnect for the design of unconventional antennas
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards graceful aging degradation in NoCs through an adaptive routing algorithm
Proceedings of the 49th Annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A graph-based approach to optimal scan chain stitching using RTL design descriptions
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
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Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.KEY FEATURES* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.* Practical problems at the end of each chapter for students.