Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Longest path selection for delay test under process variation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Path delay test compaction with process variation tolerance
Proceedings of the 42nd annual Design Automation Conference
A dynamic test compaction procedure for high-quality path delay testing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Propagation delay fault: a new fault model to test delay faults
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Estimation of delay test quality and its application to test generation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 45th annual Design Automation Conference
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Path selection for monitoring unexpected systematic timing effects
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Proceedings of the 2009 International Conference on Computer-Aided Design
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testability driven statistical path selection
Proceedings of the 48th Design Automation Conference
Order statistics for correlated random variables and its application to at-speed testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Testing the longest path passing through each gate is important to detect small localized delay defects at a gate, e.g. resistive opens or resistive shorts. In this paper we present ATPG techniques to automatically determine the longest testable path passing through a gate or wire in the circuit without first listing all long paths passing through it. This technique is based on a graph traversal algorithm that can traverse all paths of a given length in a weighted directed acyclic graph. Experimental results for ISCAS benchmarks are also presented.