Line coverage of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Performance sensitivity analysis using statistical method and its applications to delay
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Introduction to Algorithms
Transition Fault Simulation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases
Proceedings of the 40th annual Design Automation Conference
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
On test coverage of path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Generation for Multiple-Threshold Gate-Delay Fault Model
ATS '01 Proceedings of the 10th Asian Test Symposium
An Efficient Method to Identify Untestable Path Delay Faults
ATS '01 Proceedings of the 10th Asian Test Symposium
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the fault coverage of gate delay fault detecting tests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
Functions for Quality Transition Fault Tests
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Test set enhancement for quality transition faults using function-based methods
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Quality Transition Fault Tests Suitable for Small Delay Defects
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Evaluation of the statistical delay quality model
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Timing-reasoning-based delay fault diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Estimation of delay test quality and its application to test generation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unified submodular framework for multimodal IC Trojan detection
IH'10 Proceedings of the 12th international conference on Information hiding
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensitizable path. In the ATPG process, we utilize an efficient false-path pruning technique to identify the longest sensitizable path through each fault site. We demonstrate that our new SAT-based ATPG can be orders-of-magnitude faster than a commercial ATPG tool. To demonstrate the quality of the tests generated by our approach, we compare its resulting test set to three other test sets: a single-detection transition fault test set, a multiple-detection transition fault test set, and a traditional critical path test set added to the single-detection set. The superiority of our approach is demonstrated through various experiments based on statistical delay simulation and defect injection using benchmark circuits.