Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Sequential logic path delay test generation by symbolic analysis
ATS '95 Proceedings of the 4th Asian Test Symposium
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Functions for Quality Transition Fault Tests
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
IEEE Design & Test
Efficient identification of (critical) testable path delay faults using decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Compact high quality test sets to detect small delay defects can be generated using the transition fault model by insisting that events are activated and propagated only along the critical paths for each transition fault, implicitly kept in a zero-suppressed binary decision diagram. This paper shows how to implicitly generate test functions for the described high quality transition fault model. The novelty of the method relies on a multivalued algebra that is used to generate the test functions with a single circuit traversal.