Towards finding path delay fault tests with high test efficiency using ZBDDs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Quality Transition Fault Tests Suitable for Small Delay Defects
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implicit identification of non-robustly unsensitizable paths
ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
Low-power multi-core ATPG to target concurrency
Integration, the VLSI Journal
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Techniques to prioritize paths for diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Identification of delay measurable PDFs using linear dependency relationships
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a novel framework to identify all the testable and untestable path delay faults (PDFs) in a circuit. The method uses a combination of decision diagrams for manipulating PDFs as well as Boolean functions. The approach benefits from processing partial paths or fanout-free segments in the circuit rather than the entire path. The methodology is modified to identify all testable critical PDFs under the bounded delay fault model. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology outperforms any existing method for identifying testable PDFs. Its scalability by focusing on critical PDFs is demonstrated by experimenting on very path-intensive benchmarks.