Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
BiTeS: a BDD based test pattern generator for strong robust path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
Test generation for primitive path delay faults in combinational circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
A Statistical Model for Delay-Fault Testing
IEEE Design & Test
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Bounding Circuit Delay by Testing a Very Small Subset of Paths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Exact Grading of Multiple Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe
An Improved Method for Identifying Linear Dependencies in Path Delay Faults
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Enhanced Identification of Strong Robustly Testable Paths
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Efficient identification of (critical) testable path delay faults using decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Recently several methods have been presented to measure the delay of a small set of path delay faults (PDFs), known as a basis set which is used to compute the delays of PDFs. All methods assume that the basis consists of strong robustly tested PDFs because their delays can be measured. This paper presents procedures to identify measurable PDFs whose delays otherwise could not be measured by traditional strong robust sensitization. Path measurement techniques that conditer the bounded delay model allow us to compute the delays of almost all PDFs in existing benchmarks.