Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Bounding Circuit Delay by Testing a Very Small Subset of Paths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Identification of delay measurable PDFs using linear dependency relationships
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip delay measurement technique using signature registers for small-delay defect detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The use of linear dependency relationships among path delay faults (PDFs) is an effective way to determine circuit timing characteristics. The proposed approach improves the performance of performing a linear dependency check by accelerating the Gauss elimination process. This paper presents new algorithms to represent a PDF with respect to a testable set as well as a methodology to calculate the delays of all critical sensitizable PDFs while testing only a small subset of testable PDFs. In contrast to a previous implicit method, the proposed method guarantees that each sensitizable fault can be represented as a linear combination of tested faults but its time performance can be significantly improved when combined with such implicit methods.