What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
An Improved Method for Identifying Linear Dependencies in Path Delay Faults
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Exploring linear structures of critical path delay faults to reduce test efforts
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Extraction of statistical timing profiles using test data
Proceedings of the 44th annual Design Automation Conference
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Identification of delay measurable PDFs using linear dependency relationships
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip delay measurement technique using signature registers for small-delay defect detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Paths in a circuit share many lines and gates and hence, under specific assumptions, path delays are linearly related to each other. The delays of all the paths in a circuit can be expressed as a linear combination of the delays of a small subset of paths called the basis path set.In this paper we present a testing methodology and efficient algorithms to establish an upper bound (in most cases greater than the circuit clock period) on the circuit delay by testing only the paths in the basis path set. Since the size of the basis path set has been shown to be at most linear in the size of the circuit, this technique has the potential of drastically reducing the number of paths that have to be tested. Experimental results for benchmark circuits are given.