A variable observation time method for testing delay faults
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient diagnosis of path delay faults in digital logic circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Performance sensitivity analysis using statistical method and its applications to delay
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
A Systematic Approach for Diagnosing Multiple Delay Faults
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A new path-oriented effect-cause methodology to diagnose delay failures
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Proceedings of the 40th annual Design Automation Conference
Diagnosis of parametric path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Adaptive Techniques for Improving Delay Fault Diagnosis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Bounding Circuit Delay by Testing a Very Small Subset of Paths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Diagnosis of Delay Defects Using Statistical Timing Models
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
On Diagnosing Path Delay Faults in an At-Speed Environment
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
An Adaptive Path Delay Fault Diagnosis Methodology
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Path delay fault diagnosis in combinational circuits with implicit fault enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An implicit path-delay fault diagnosis methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-fault diagnosis using timing information
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Diagnosis of transition fault clusters
Proceedings of the 48th Design Automation Conference
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes
Proceedings of the Conference on Design, Automation and Test in Europe
An on-chip delay measurement technique using signature registers for small-delay defect detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we propose a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the linear constraints solved by a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. Besides, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. Three main features of the proposed method are that: 1) it does not assume any delay fault model; 2) it derives diagnosis results directly from test data; and 3) it is able to diagnose failures caused by multiple delay defects. These features make our proposed method more realistic on solving the real problems occurring in the manufacturing process. In the experimental results, for most cases of injecting 5% of the longest path delay, the probabilities are over 90% for locating faulty segments within the list of top-ten suspects, and the average rankings, that is often referred to as first hit rank (FHR), which is defined as the rank of the first hit of the defect in the ranking list, are among the top five suspect locations for single fault injection. In the experimental results of multiple faults injection, the average FHRs are also lower than 5 for all cases of injecting 1% of the longest path delay.