A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Probabilistic mixed-model fault diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new path-oriented effect-cause methodology to diagnose delay failures
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
Efficiency Improvements for Multiple Fault Diagnosis of Combinational Circuits
ATS '01 Proceedings of the 10th Anniversary Compendium of Papers from Asian Test Symposium 1992-2001
A diagnosability metric for parametric path delay faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Adaptive Techniques for Improving Delay Fault Diagnosis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
POIROT1: A Logic Fault Diagnosis Tool and Its Applications
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple Fault Diagnosis Using n-Detection Tests
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '07 Proceedings of the 12th IEEE European Test Symposium
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
Multiple defect diagnosis using no assumptions on failing pattern characteristics
Proceedings of the 45th annual Design Automation Conference
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing-aware multiple-delay-fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On error correction in macro-based circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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When multiple defects are present in a chip, the defects may be distributed randomly, or clustered in certain areas. When a large number of defects are clustered in an area, the possibility that their effects will interact is stronger than when they are fewer and further apart. This paper demonstrates that this reduces the accuracy of fault diagnosis based on single faults. Specifically, with the same diagnosis procedure based on single faults and the same number of faults injected into a circuit, random subsets of transition faults are easier to diagnose than clusters. The paper also develops a fault diagnosis procedure based on single faults that provides more accurate results for large clusters. The procedure considers limited numbers of double transition faults in order to obtain better matches for the cluster being diagnosed.