Fundamentals of Computer Alori
Fundamentals of Computer Alori
Multiple fault diagnosis in combinational networks.
Multiple fault diagnosis in combinational networks.
Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
Minimal Fault Tests for Combinational Networks
IEEE Transactions on Computers
On Necessary and Sufficient Conditions for Multiple Fault Undetectability
IEEE Transactions on Computers
On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Modeling the unknown! Towards model-independent fault and error diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new path-oriented effect-cause methodology to diagnose delay failures
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ATS '95 Proceedings of the 4th Asian Test Symposium
Multiple fault diagnosis in sequential circuits using sensitizing sequence pairs
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Test Application
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Making Cause-Effect Cost Effective: Low-Resolution Fault Dictionaries
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits
IEEE Transactions on Computers
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
IEICE - Transactions on Information and Systems
S/390 G5 CMOS microprocessor diagnostics
IBM Journal of Research and Development
Diagnosis of integrated circuits with multiple defects of arbitrary characteristics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
On clustering of undetectable single stuck-at faults and test quality in full-scan circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Selection of a fault model for fault diagnosis based on unique responses
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis of experimental results on functional testing and diagnosis of complex circuits
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On multiple fault coverage and aliasing probability measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of transition fault clusters
Proceedings of the 48th Design Automation Conference
Diagnostic Test Set Minimization and Full-Response Fault Dictionary
Journal of Electronic Testing: Theory and Applications
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In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A fault situation specifies faulty as well as fault-free lines. Other applications include identifying the existence of nonstuck faults in N* and determination of faults not detected by a given test, including redundant faults. The latter application allows for the generation of tests for multiple faults without performing fault enumeration.