An advanced diagnostic method for delay faults in combinational faulty circuits
Journal of Electronic Testing: Theory and Applications
Delay fault diagnosis in sequential circuits based on path tracing
Integration, the VLSI Journal
A deductive technique for diagnosis of bridging faults
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient diagnosis of path delay faults in digital logic circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
A new path-oriented effect-cause methodology to diagnose delay failures
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A non-enumerative path delay fault simulator for sequential circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
On variable clock methods for path delay testing of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 40th annual Design Automation Conference
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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A new methodology is developed in this paper for identifyingpossible path delay faults through at-speed testing of sequentialnon-scan circuits. In the past, different techniques havebeen proposed for diagnosing delay faults in sequential circuitsthrough variable clock control techniques. These techniquesare, however, not readily applicable to commercialhigh-performance ICs. We propose new techniques based oncritical-path tracing which can be used to locate slow pathsin sequential circuits. Strategies have been developed to improvethe diagnostic resolution, which involve deducing internalstate values from the observed circuit outputs and thedetection of fault-free circuit paths. Results of experimentson the ISCAS89 sequential benchmark suite are finally discussed.