A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning
IEEE Transactions on Computers
Test challenges for deep sub-micron technologies
Proceedings of the 37th Annual Design Automation Conference
Performance sensitivity analysis using statistical method and its applications to delay
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Test Application
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Diagnosing realistic bridging faults with single stuck-at information
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path delay fault diagnosis and coverage-a metric and an estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 40th annual Design Automation Conference
Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Delay Fault Diagnosis for Non-Robust Test
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Test Consideration for Nanometer-Scale CMOS Circuits
IEEE Design & Test
Timing-reasoning-based delay fault diagnosis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design-silicon timing correlation: a data mining perspective
Proceedings of the 44th annual Design Automation Conference
Statistical diagnosis of unmodeled systematic timing effects
Proceedings of the 45th annual Design Automation Conference
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Adaptive Debug and Diagnosis Without Fault Dictionaries
Journal of Electronic Testing: Theory and Applications
A statistical diagnosis approach for analyzing design-silicon timing mismatch
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay defect diagnosis and traditional logic defect diagnosis. We propose different diagnosis algorithms, and evaluate their performance via statistical defect injection and statistical delay fault simulation. With a statistical timing analysis framework developed in the past, we demonstrate the new concepts in delay defect diagnosis, and discuss experimental results based upon benchmark circuits.