Exact evaluation of diagnostic test resolution
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Algorithms for current monitor based diagnosis of bridging and leakage faults
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An algorithm for diagnosing two-line bridging faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
On error correction in macro-based circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Diagnosis of realistic bridging faults with single stuck-at information
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On the generation of small dictionaries for fault location
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Failure Diagnosis of Structured VLSI
IEEE Design & Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Fault Location with Current Monitoring
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Diagnostic Fault Simulation of Sequential Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Comparison of Defect Models for Fault Location with IDDQ Measurements
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Coupling Electron-Beam Probing with Knowledge-Based Fault Localization
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Fault diagnosis based on effect-cause analysis: An introduction
DAC '80 Proceedings of the 17th Design Automation Conference
On the effects of test compaction on defect coverage
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Diagnosis oriented test pattern generation
EURO-DAC '90 Proceedings of the conference on European design automation
Exclusive Test and its Applications to Fault Diagnosis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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We propose a method of fault diagnosis at the chip level that reduces the number of simulations required to locate defect site(s) by logically partitioning the circuit into subcircuits. Candidate subcircuits that potentially contain the defect site(s) are identified and further partitioned until the defect site is located with the required resolution. Both stuck-at faults and nonfeedback bridging faults are considered as target fault models to represent defects. At the base of the fault location procedure is a procedure to identify subcircuits that potentially contain the fault site. This procedure is matched to the fault model being considered, thus allowing the same partitioning scheme to be applied to various fault models. The procedure presented here is applicable to combinational and fully scanned sequential circuits. Experimental results are presented to demonstrate the effectiveness of circuit partitioning in reducing the number of fault simulations required to locate a fault.