COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits

On the over-specification problem in sequential ATPG algorithms

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Generation of deterministic test patterns by minimal basic test sets

EURO-DAC '92 Proceedings of the conference on European design automation

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

DAC '93 Proceedings of the 30th international Design Automation Conference

Design-for-testability for path delay faults in large combinatorial circuits using test-points

DAC '94 Proceedings of the 31st annual Design Automation Conference

Aliasing Computation Using Fault Simulation with Fault Dropping

IEEE Transactions on Computers

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

IEEE Transactions on Computers - Special issue on fault-tolerant computing

A formal non-heuristic ATPG approach

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Pattern generation for a deterministic BIST scheme

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

On Dictionary-Based Fault Location in Digital Logic Circuits

IEEE Transactions on Computers

Test set compaction algorithms for combinational circuits

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning

IEEE Transactions on Computers

A Heuristic Measure to Maximize Detected Faults per Test

Journal of Electronic Testing: Theory and Applications

Efficient Techniques for Dynamic Test Sequence Compaction

IEEE Transactions on Computers

An algorithm to reduce test application time in full scan designs

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

On the generation of small dictionaries for fault location

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Optimal Zero-Aliasing Space Compaction of Test Responses

IEEE Transactions on Computers

On identifying don't care inputs of test patterns for combinational circuits

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Testing ICs: Getting to the Core of the Problem

Computer

Generating Tests for Delay Faults in Nonscan Circuits

IEEE Design & Test

Testing of Fault-Tolerant Hardware Through Partial Control of Inputs

IEEE Transactions on Computers

Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability

IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing

Accumulator based deterministic BIST

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Deterministic Pattern Generation for Weighted Random Pattern Testing

EDTC '96 Proceedings of the 1996 European conference on Design and Test

A genetic approach to test application time reduction for full scan and partial scan circuits

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

On n-detection test sequences for synchronous sequential circuits

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Tailoring ATPG for Embedded Testing

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Putting the Squeeze on Test Sequences

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Test Width Compression for Built-In Self Testing

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution

IEEE Transactions on Computers

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Dynamic Test Compaction for Bridging Faults

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Two dimensional reordering of functional test data for compression by ATE

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

On test generation by input cube avoidance

Proceedings of the conference on Design, automation and test in Europe

Aliasing-Free Compaction In Testing Cores-Based System-On-Chip (SOC) Using Compatibility Of Response Data Outputs

Journal of Integrated Design & Process Science

A low-cost BIST scheme for test vector embedding in accumulator-generated sequences

VLSI Design

Dynamic test compaction for a random test generation procedure with input cube avoidance

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Definition and application of approximate necessary assignments

Proceedings of the 19th ACM Great Lakes symposium on VLSI

State persistence: a property for guiding test generation

Proceedings of the 19th ACM Great Lakes symposium on VLSI

Forward-looking reverse order fault simulation for n-detection test sets

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Deterministic broadside test generation for transition path delay faults

Proceedings of the 20th symposium on Great lakes symposium on VLSI

On clustering of undetectable single stuck-at faults and test quality in full-scan circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe

Enhancing testability in architectural design for the new generation of core-based embedded systems

HASE'04 Proceedings of the Eighth IEEE international conference on High assurance systems engineering

ATPG for heat dissipation minimization during test application

ITC'94 Proceedings of the 1994 international conference on Test

A test clock reduction method for scan-designed circuits

ITC'94 Proceedings of the 1994 international conference on Test

Efficient test response compression for multiple-output circuits

ITC'94 Proceedings of the 1994 international conference on Test

Reduced scan shift: a new testing method for sequential circuits

ITC'94 Proceedings of the 1994 international conference on Test

Fault tolerant systems design in VLSI using data compression under constraints of failure probabilities: overview and status

CIMMACS'07 Proceedings of the 6th WSEAS international conference on Computational intelligence, man-machine systems and cybernetics

Random test generation with input cube avoidance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A new scheme of test data compression based on equal-run-length coding (ERLC)

Integration, the VLSI Journal

Altera max plus II development environment in fault simulation and test implementation of embedded

IWDC'04 Proceedings of the 6th international conference on Distributed Computing

Implementation of embedded cores-based digital devices in JBits java simulation environment

CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology