Efficient test response compression for multiple-output circuits

Authors:
Krishnendu Chakrabarty;John P. Hayes
Affiliations:
Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI;Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

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Abstract

A major obstacle to achieving high fault coverage in built-in self testing (BIST) methods that employ response compression is aliasing, which occurs when a faulty circuit's signature maps to the fault-free signature. Another problem with many compression methods is that they are inefficient for multiple-output circuits. We present data showing that in most cases, faults are sensitized to an odd number of outputs, even when reduced test sets are used. This suggests that odd-parity detection alone provides very high fault coverage. We then introduce several systematic design techniques that guarantee zero-aliasing compression for single stuck-line faults in multiple-output circuits. We present the results of applying this approach to the ISCAS combinational benchmark circuits using both reduced and pseudorandom test sets. Our experiments show that very high fault coverage (up to 100%) can ibe achieved with small test sets and low hardware overhead.