Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
A unified view of test compression methods
IEEE Transactions on Computers
Bounding Signal Probabilities in Combinational Circuits
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Group Theoretic Signature Analysis
IEEE Transactions on Computers
Shift Register Sequences
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Simple Bounds on Serial Signature Analysis Aliasing for Random Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa
IEEE Transactions on Computers
Parallel Signature Analysis Design with Bounds on Aliasing
IEEE Transactions on Computers
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
Built-in-self-test with an alternating output
Proceedings of the conference on Design, automation and test in Europe
A Note on Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Design of CAECC - Cellular Automata Based Error Correcting Code
IEEE Transactions on Computers
CA-Based Byte Error-Correcting Code
IEEE Transactions on Computers
Can Nonlinear Compactors Be Better than Linear Ones?
IEEE Transactions on Computers
Zero-Aliasing for Modeled Faults
IEEE Transactions on Computers
Aliasing Error for a Mask ROM Built-In Self-Test
IEEE Transactions on Computers
IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Journal of Integrated Design & Process Science
GLFSR: a new test pattern generator for built-in-self-test
ITC'94 Proceedings of the 1994 international conference on Test
Efficient test response compression for multiple-output circuits
ITC'94 Proceedings of the 1994 international conference on Test
Altera max plus II development environment in fault simulation and test implementation of embedded
IWDC'04 Proceedings of the 6th international conference on Distributed Computing
Implementation of embedded cores-based digital devices in JBits java simulation environment
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
| Hi-index | 15.02 |
A general framework for shift register-based signature analysis is presented, and a mathematical model for this framework-based on coding theory-is developed. There are two key features of this formulation, first, it allows for uniform treatment of LFSR, MISR, and multiple MISR-based signature analyzer. In addition, using this formulation, a new compression scheme for multiple output CUT is proposed. This scheme, referred to as multiinput LFSR, has the potential to achieve better aliasing than other schemes such as the multiple MISR scheme of comparable hardware complexity. Several results on aliasing are presented, and certain known results are shown to be direct consequences of the formulation. Also developed are error models that take into account the circuit topology and the effect of faults at the outputs. Using these models, exact closed-form expressions for aliasing probability are developed. A closed-form aliasing expression for MISR under an independent error model is provided.