Optimizing error masking in BIST by output data modification
Journal of Electronic Testing: Theory and Applications
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
BIST with negligible aliasing through random cover circuits
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An apparatus for pseudo-deterministic testing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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A new compaction technique based on signature analysis is presented. Rather than comparing the final signature with the expected one after the test is completed, the binary output of the MISA is converted into an alternating binary signal by two simple cover circuits. An error is indicated whenever the alternation of the output signal is disturbed. This technique results in a higher fault coverage, improved fault diagnosis capability, a greater test autonomy in core-based designs, and early fault notification.