Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
BIST hardware generator for mixed test scheme
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Transformed pseudo-random patterns for BIST
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A novel pattern generator for near-perfect fault-coverage
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Deterministic BIST with Multiple Scan Chains
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Optimal hardware pattern generation for functional BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Deterministic BIST with Partial Scan
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Minimized Power Consumption for Scan-Based BIST
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Circuit partitioning for efficient logic BIST synthesis
Proceedings of the conference on Design, automation and test in Europe
Built-in-self-test with an alternating output
Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Embedded test control schemes for compression in SOCs
Proceedings of the 39th annual Design Automation Conference
A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
Journal of Electronic Testing: Theory and Applications
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Journal of Electronic Testing: Theory and Applications
Test Set Embedding Based on Phase Shifters
EDCC-4 Proceedings of the 4th European Dependable Computing Conference on Dependable Computing
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
A scan BIST generation method using a markov source and partial bit-fixing
Proceedings of the 40th annual Design Automation Conference
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Deterministic Test Sets in BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression and test time reduction using an embedded microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Journal of Electronic Testing: Theory and Applications
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Journal of Electronic Testing: Theory and Applications
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
X-masking during logic BIST and its impact on defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan-BIST based on cluster analysis and the encoding of repeating sequences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Column-matching based mixed-mode test pattern generator design technique for BIST
Microprocessors & Microsystems
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Study on Expansion of Convolutional Compactors over Galois Field
IEICE - Transactions on Information and Systems
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
IEICE - Transactions on Information and Systems
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and verification of the IBM system z10 I/O subsystem chips
IBM Journal of Research and Development
Reducing the storage requirements of a test sequence by using a background vector
Proceedings of the Conference on Design, Automation and Test in Europe
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Test data compression using efficient bitmask and dictionary selection methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Increasing embedding probabilities of RPRPs in RIN based BIST
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Journal of Electronic Testing: Theory and Applications
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A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which feeds a scan path has to be modified only at a few bits in order to transform the random patterns into a complete test set. These modifications may be implemented by a bit-flipping function which has the LFSR-state as an input, and flips the value shifted into the scan path at certain times. A procedure is described for synthesizing the additional bit-flipping circuitry, and the experimental results indicate that this mixed-mode BIST scheme requires less hardware for complete fault coverage than all the other scan-based BIST approaches published so far.