Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Cellular Automata for Weighted Random Pattern Generation
IEEE Transactions on Computers
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Hardware-optimal test register insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
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