Group Properties of Cellular Automata and VLSI Applications
IEEE Transactions on Computers
A method for generating weighted random test pattern
IBM Journal of Research and Development
A fault simulation method: parallel pattern critical path tracing
Journal of Electronic Testing: Theory and Applications
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Parallel computation of non-deterministic algorithms in vlsi
Parallel computation of non-deterministic algorithms in vlsi
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
A scalable test structure for multicore chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 14.98 |
Fault testing random-pattern-resistant circuits requires that BIST (built-in self-test) techniques generate large numbers of pseudorandom patterns. To shorten these long test lengths, this study describes a cellular automata-based method that efficiently generates weighted pseudorandom BIST patterns. This structure, called a weighted cellular automaton (WCA), uses no external weighting logic. The design algorithm MWCARGO combines generation of the necessary weight sets and design of the WCA. In this study, WCA pattern generators designed by MWCARGO achieved 100 percent coverage of testable stuck-at faults for benchmark circuits with random-pattern-resistant faults. The WCA applies complete tests much faster than existing test-per-scan techniques. At the same time, the hardware overhead of WCA proves to be competitive with that of current test-per-clock schemes.