Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Minimal cost one-dimensional linear hybrid cellular automata of degree through 500
Journal of Electronic Testing: Theory and Applications
Cellular Automata for Weighted Random Pattern Generation
IEEE Transactions on Computers
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High Speed Ring Generators and Compactors of Test Data
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
An efficient design of non-linear CA based PRPG for VLSI circuit testing
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores
ATS '04 Proceedings of the 13th Asian Test Symposium
High Performance Dense Ring Generators
IEEE Transactions on Computers
Synthesis of one-dimensional linear hybrid cellular automata
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GLFSR-a new test pattern generator for built-in-self-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of hierarchical cellular automata for on-chip test pattern generator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pseudorandom number generation with self-programmable cellular automata
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper reports an efficient synthesis scheme for pseudorandom pattern generators (PRPGs) of arbitrary length. The n-bit PRPG, synthesized in linear time (O(n)), generates quality pseudorandom patterns leading to a highly efficient test logic for the very-large-scale integration (VLSI) circuit. The cascadable structure of proposed n-cell PRPG is utilized to construct the (n + 1)-cell PRPG, in two time steps, without sacrificing the pseudorandomness quality. This eases the design of on-chip test pattern generators for the system-on-achip implementing multiple cores. It avoids the requirement of disparate test hardware for different cores and thereby ensures drastic reduction in the cost of test logic. The effective characterization of nonlinear cellular automata (CA) provides the foundation of such a design. Extensive experimentation confirms the better efficiency of the proposed test structure compared to that of the conventional designs, developed around maximal length CA/linear feedback shift register of O(n3) complexity.