Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Discrete logarithms: a parallel pseudorandom pattern generator analysis method
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers - Special issue on fault-tolerant computing
10.2 Design of Phase Shifters for BIST Applications
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Decompression of test data using variable-length seed LFSRs
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Pseudorandom Arrays for Built-In Tests
IEEE Transactions on Computers
Cellular automata as a built in self test structure
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Structure Verification of Logical BIST: Problems and Solutions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DESIGN OF COMPACTORS FOR SIGNATURE-ANALYZERS IN BUILT-IN SELF-TEST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Synthesis of Pattern Generators Based on Cellular Automata with Phase Shifters
ITC '99 Proceedings of the 1999 IEEE International Test Conference
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A unified method for phase shifter computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A seed selection procedure for LFSR-based random pattern generators
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Proceedings of the conference on Design, automation and test in Europe
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable test structure for multicore chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The paper introduces a new algorithm for the automatedsynthesis of phase shifters - circuits used to remove effectsof structural dependencies featured by two-dimensionaltest generators. The algorithms presented in the papersynthesize in a time-efficient manner very large and fastphase shifters for built-in self-test environment, with guaranteedminimal phaseshifts between scan chains, and verylow delay and area of virtually one 2-way XOR gate perchannel.