Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Design considerations for parallel pseudorandom pattern generators
Journal of Electronic Testing: Theory and Applications
Discrete logarithms: a parallel pseudorandom pattern generator analysis method
Journal of Electronic Testing: Theory and Applications
Pseudorandom Arrays for Built-In Tests
IEEE Transactions on Computers
Deterministic BIST with Multiple Scan Chains
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Synthesis of Pattern Generators Based on Cellular Automata with Phase Shifters
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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The paper presents novel systematic design techniques for the automated synthesis of phase shifters - circuits used to remove effects of structural dependencies featured by test generators driving parallel scan chains. As shown in the paper, it is possible to synthesize very large and fast phase shifters for BIST applications with guaranteed phaseshifts between scan chains and very small number of gates per channel.