Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
Introducing Core-Based System Design
IEEE Design & Test
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Testing Core-Based Systems: A Symbolic Methodology
IEEE Design & Test
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
10.2 Design of Phase Shifters for BIST Applications
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Efficient Generation of Statistically Good Pseudonoise by Linearly Interconnected Shift Registers
IEEE Transactions on Computers
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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The paper presents a new modular logic BIST architecturefor intellectual property (IP) cores and block-orienteddesign methodology. The scheme involves two-step developmentprocess: design and analysis of BIST-ready IPcores and system integration. A BIST-ready core has insertedscan chains, test points, a repeater with phaseshifter to perform serial to parallel conversion of test vectors,and a space-time test-response compactor. It is alsosimulated to determine its fault coverage and signature fora specified configuration of BIST hardware. Particulars ofa method to compute the composite signature for the wholedesign based on signatures representing individual coresare presented altogether with a new technique to expandtest vectors. At the system ASIC level, the paper demonstrateshow multiple cores can be seamlessly integratedand then tested in exactly the same manner as they wereanalyzed by sharing the same BIST controller.