Addressable Test Ports An Approach to Testing Embedded Cores

Authors:
Lee Whetsel
Affiliations:
-
Venue:
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Year:
1999

Citing 9
Cited 18

Testing the monster chip

IEEE Spectrum
A 256Meg SDRAM BIST for Disturb Test Application

Proceedings of the IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs

ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modular logic built-in self-test for IP cores

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Core test connectivity, communication, and control

ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example

ITC '99 Proceedings of the 1999 IEEE International Test Conference

System chip test: how will it impact your design?

Proceedings of the 37th Annual Design Automation Conference
Testing TAPed cores and wrapped cores with the same test access mechanism

Proceedings of the conference on Design, automation and test in Europe
Test of future system-on-chips

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On Concurrent Test of Core-Based SOC Design

Journal of Electronic Testing: Theory and Applications
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

Journal of Electronic Testing: Theory and Applications
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application

Journal of Electronic Testing: Theory and Applications
On Using IEEE P1500 SECT for Test Plug-n-Play

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Unsafe Board States During PC-Based Boundary-Scan Testing

ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Token Scan Architecture for Low Power Testing

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Time Domain Multiplexed TAM: Implementation and Comparison

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST

IEEE Transactions on Computers
A new design-for-test technique for reducing SOC test time

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip

Integration, the VLSI Journal
STEAC: a platform for automatic SOC test integration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient link controller for test access to IP core-based embedded system chips

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

Intellectual property (IP) core reuse is an emerging designstyle that will significantly accelerate the complexity of ICs. IPcores are predesigned circuit functions that can be selected froma library and integrated into system ICs to quickly providehighly complex silicon solutions. Low cost, efficient testing ofsystem ICs designed with IP cores will be challenging.