Evaluation of a MULTIFIT-based scheduling algorithm
Journal of Algorithms
Multiprocessor scheduling: combining LPT and MULTIFIT
Discrete Applied Mathematics
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
The Role of Test Protocols in Testing Embedded-Core-Based System ICs
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Challenges in testing core-based system ICs
IEEE Communications Magazine
Test Bus Sizing for System-on-a-Chip
IEEE Transactions on Computers
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The design and optimization of SOC test solutions
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures
Journal of Electronic Testing: Theory and Applications
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of reconfigurable access wrappers for embedded core based SoC test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
IEEE Transactions on Computers
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Wrapper Design for Testing IP Cores with Multiple Clock Domains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Note on System-on-Chip Test Scheduling Formulation
Journal of Electronic Testing: Theory and Applications
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
Proceedings of the 42nd annual Design Automation Conference
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Test environment for embedded cores-based system-on-chip (soc): development and methodologies
MIC'06 Proceedings of the 25th IASTED international conference on Modeling, indentification, and control
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
Integration, the VLSI Journal
Optimized integration of test compression and sharing for SOC testing
Proceedings of the conference on Design, automation and test in Europe
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
IEICE - Transactions on Information and Systems
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
IEICE - Transactions on Information and Systems
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
IEEE standard 1500 compatible delay test framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Multi-temperature testing for core-based system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Wrapper design for multifrequency IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
| Hi-index | 0.01 |
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (TAM), the core test wrapper forms the test access infrastructure to embedded reusable cores. Various company-internal as well as industry-wide standardized but scalable wrappers have been proposed. This paper deals with the design of such core test wrappers. It gives a general architecture for wrappers, and describes how a wrapper can be built up from a library of wrapper cells which are selected on basis of the terminal types of the core. We show that the ordering and partitioning of wrapper cells and core-internal scan chains over TAM chains determines the test time of the core. A heuristic approach for theNP-hard problem of partitioning the TAM chain items for minimal test time is presented and its usage is illustratedby means of an example. Finally we sketch how wrapper generation and verification can be automated.