Complexity of scheduling parallel task systems
SIAM Journal on Discrete Mathematics
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Open Shop Scheduling to Minimize Finish Time
Journal of the ACM (JACM)
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Scheduling independent tasks to reduce mean finishing time
Communications of the ACM
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling Algorithms
Journal of Electronic Testing: Theory and Applications
Optimal Processor Assignment for a Class of Pipelined Computations
IEEE Transactions on Parallel and Distributed Systems
Test wrapper and test access mechanism co-optimization for system-on-chip
Proceedings of the IEEE International Test Conference 2001
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Defect-Oriented Test Scheduling
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formulating SoC test scheduling as a network transportation problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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While many different formulations of the embedded core test scheduling problem (ECTSP) have been proposed in test literature recently, a single unified presentation of ECTSP in terms of conventional scheduling patterns has been lacking. There exists a large body of literature on multi-processor scheduling which can be directly applied to ECTSP; in this paper the author presents an introduction to scheduling notation and demonstrates the mapping between many important test scheduling problems like power-constrained, precedence constrained, and defect-oriented scheduling to conventional multi-processor job scheduling problems. Two examples are presented to illustrate this mapping. This unified presentation should make the existing body of knowledge in Operations Research scheduling research easily accessible to test engineers and test automation tool developers.