Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
A scheme for overlaying concurrent testing of VLSI circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
ATS '00 Proceedings of the 9th Asian Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Minimizing concurrent test time in SoC's by balancing resource usage
Proceedings of the 12th ACM Great Lakes symposium on VLSI
The design and optimization of SOC test solutions
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Optimization of Test Accesses with a Combined BIST and External Test Scheme
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
A Note on System-on-Chip Test Scheduling Formulation
Journal of Electronic Testing: Theory and Applications
Rapid Generation of Thermal-Safe Test Schedules
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Test time minimization for hybrid BIST of core-based systems
Journal of Computer Science and Technology
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Classical scheduling approaches are applied here toovercome the problem of unequal-length block-test schedulingunder power dissipation constraints. List schedulinglikeapproaches are proposed first as greedy algorithmsto tackle the fore mentioned problem. Then, distributiongraphbased approaches are described in order to achievebalanced test concurrency and test power dissipation. Anextended tree growing technique is also used in combinationwith these classical approaches in order to improvethe test concurrency having assigned power dissipation limits.A comparison between the results of the test schedulingexperiments highlights the advantages and disadvantagesof applying different classical scheduling algorithms to the power-constrained test scheduling problem.