Scheduling tests for VLSI systems under power constraints

Authors:
Richard M. Chou;Kewal K. Saluja;Vishwani D. Agrawal
Affiliations:
Univ. of Wisconsin, Madison;Univ. of Wisconsin, Madison;Bell Labs, Lucent Technologies, Murray Hill, NJ
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1997

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Abstract

This paper considers the problem of testing VLSI integrated circuits in minimum time without exceeding their power ratings during test. We use a resource graph formulation for the test problem. The solution requires finding a power-constrained schedule of tests. Two formulations of this problem are given as follows: (1) scheduling equal length tests with power constraints and (2) scheduling unequal length tests with power constraints. Optimum solutions are obtained for both formulations. Algorithms consist of four basic steps. First, a test compatibility graph is constructed from the resource graph. Second, the test compatibility graph is used to identify a complete set of time compatible tests with power dissipation information associated with each test. Third, from the set of compatible tests, lists of power compatible tests are extracted. Finally, a minimum cover table approach is used to find an optimum schedule of power compatible tests.