Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and minimization of test time in a combined BIST and external test approach
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Scheduling Algorithms
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Introducing Core-Based System Design
IEEE Design & Test
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
Test Resource Partitioning and Optimization for SOC Designs
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Hybrid BIST Architecture and its Optimization for SoC Testing
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
Integrating Core Selection in the SOC Test Solution Design-Flow
ITC '04 Proceedings of the International Test Conference on International Test Conference
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of Thermal Gradients on Clock Skew and Testing
IEEE Design & Test
Power-aware SoC test planning for effective utilization of port-scalable testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-temperature testing for core-based system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
Computers and Electrical Engineering
Hi-index | 14.98 |
Test application and test design, performed to ensure the production of fault-free chips, are becoming complicated and very expensive, especially in the case of SoCs (System-on-Chip), as the number of possible faults in a chip is increasing dramatically due to the technology development. It is therefore important to take test design into consideration as early as possible in the SoC design-flow in order to develop an efficient test solution. We propose a technique for modular core-based SoCs where test design is integrated in the early design exploration process. The technique can, in contrast to previous approaches, already be used in the core selection process to evaluate the impact on the system's final test solution imposed by different design decisions. The proposed technique considers the interdependent problems of core selection, test scheduling, TAM (test access mechanism) design, test set selection, and test resource floorplanning, and minimizes a weighted cost-function based on test time and TAM routing cost, while considering test conflicts and test power limitations. Concurrent scheduling of tests is used to minimize the test application time; however, concurrent test application leads to higher activity during the testing and, hence, higher power consumption. The power consumed during testing is, in general, higher than that during normal operation since it is desirable with hyperactivity in order to maximize the number of tested faults in a minimal time. A system under test can actually be damaged during testing and, therefore, power constraints must be considered. However, power consumption is complicated to model and, often, simplistic models that focus on the global system power limit only have been proposed and used. We therefore include a novel three-level power model: system, power-grid, and core. The advantage is that the system-level power budget is met and hot-spots can be avoided both at a specific core and at certain hot-spot areas in the chip. We have implemented and compared the proposed technique with a technique that assumes already fixed cores and tests, an estimation-based approach, and a computationally expensive pseudoexhaustive method. The results from the experiments show that, by exploring different design and test alternatives, the total test cost can be reduced, the pseudoexhaustive technique cannot produce results within reasonable computational time, and the estimation-based technique cannot produce solutions with high quality. The proposed technique produces results that are near the ones produced by the pseudoexhaustive technique at computational costs that are near the costs of the estimation-based technique, i.e., it produces high-quality solutions at low computational cost.