Test Resource Partitioning and Optimization for SOC Designs

Authors:
Erik Larsson;Hideo Fujiwara
Affiliations:
Linkopings Universitet/ Nara Institute of Science and Technology;Nara Institute of Science and Technology
Venue:
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Year:
2003

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Abstract

Localized delay defects, like resistive shorts, resistiveopens, etc., can be effectively detected by testing the longesttestable path through each wire (or gate) in the circuit. Sucha delay test set is referred to as a longest-path-per-wire testset. ...