Low-Area Wrapper Cell Design for Hierarchical SoC Testing

Authors:
Kyuchull Kim;Kewal K. Saluja
Affiliations:
Department of Computer Engineering, Dankook University, Gyeonggi-do, South Korea 448-701;Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, USA 53706-1691
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2009

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Abstract

System-on-chip (SoC) integrated circuits are designed and fabricated with multiple levels of hierarchy. However, most previous works on wrapper design, test access mechanism optimization and test scheduling did not take care of the hierarchy properly, thus the corresponding test schedules were often invalid for SoCs with hierarchical cores. We propose a low-area wrapper cell design which can treat SoCs with hierarchy properly and allows simultaneous testing of parent and child cores. The proposed cell uses 13%~23% less area than a recently proposed cell design in equivalent gate count. As a result we achieve up to 21% area reduction for hierarchical ITC '02 SoCs compared to the most recently proposed designs.