Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs
ATS '97 Proceedings of the 6th Asian Test Symposium
SOC Test Scheduling Using Simulated Annealing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test
ATS '04 Proceedings of the 13th Asian Test Symposium
Testing of core-based systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power-aware SoC test planning for effective utilization of port-scalable testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-Area Wrapper Cell Design for Hierarchical SoC Testing
Journal of Electronic Testing: Theory and Applications
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Hi-index | 0.00 |
This paper presents a reconfigurable union wrapper that can wrap multiple cores into a single wrapper design. Moreover, we present a test scheduling algorithm to minimize a test application time using the proposed reconfigurable union wrapper. The proposed heuristic algorithm can achieve short test application time with low computational cost compared to the conventional approaches where every core has its own wrapper. Experimental results for the ITC'02 SOC Benchmarks show the effectiveness of our approach.