On IEEE P1500's Standard for Embedded Core Test

Authors:
Erik Jan Marinissen;Rohit Kapur;Maurice Lousberg;Teresa McLaurin;Mike Ricchetti;Yervant Zorian
Affiliations:
Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands. Erik.Jan.Marinissen@philips.com;Synopsys, Inc., 455 N. Mary Avenue, Sunnyvale, CA 94087, USA. RKapur@synopsys.com;Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands. Maurice.Lousberg@philips.com;ARM, Inc., 1250 S. Capital of Texas Highway, Austin, TX 78746, USA. Teresa.McLaurin@arm.com;Intellitech Corp., 70 Main Street, Durham, NH 03824, USA. MikeR@intellitech.com;LogicVision, Inc., 101 Metro Drive, 3rd Floor, San Jose, CA 951100, USA. Zorian@logicvision.com
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2002

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Abstract

The increased usage of embedded pre-designed reusable cores necessitates a core-based test strategy, in which cores are tested as separate entities. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of core-based system chips, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its scalable wrapper architecture, its test information transfer model described in a standardized Core Test Language, and its two compliance levels. The standard is still under development, and this paper only reflects the view of six active participants of the standardization committee on its current status.