Open Shop Scheduling to Minimize Finish Time
Journal of the ACM (JACM)
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The design and optimization of SOC test solutions
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Optimization of Test Accesses with a Combined BIST and External Test Scheme
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test time minimization for hybrid BIST of core-based systems
Journal of Computer Science and Technology
Microprocessor based self schedule and parallel BIST for system-on-a-chip
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
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We present optimal solutions to the test scheduling problem for core-based systems. We show that test scheduling is equivalent to the m-processor open-shop scheduling problem and is therefore NP-complete. However, a commonly-encountered instance of this problem (m = 2) can be solved in polynomial time. For the general case (m 2), we present a mixed-integer linear programming (MILP) model for optimal scheduling and apply it to a representative core-based system using an MILP solver. We also extend the MILP model to allow optimal test set selection from a set of alternatives. Finally, we present an efficient heuristic algorithm for handling larger systems for which the MILP model may be infeasible.