A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Introducing Core-Based System Design
IEEE Design & Test
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Modifying User-Defined Logic for Test Access to Embedded Cores
Proceedings of the IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Modular logic built-in self-test for IP cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A General Purpose IDDQ Measurement Circuit
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Macro Testing: Unifying IC And Board Test
IEEE Design & Test
System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
A framework for testing core-based systems-on-a-chip
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Test scheduling for core-based systems
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Analysis and minimization of test time in a combined BIST and external test approach
DATE '00 Proceedings of the conference on Design, automation and test in Europe
CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Circuit partitioning for efficient logic BIST synthesis
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Synthesis of single-output space compactors with application to scan-based IP cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Selective-run built-in self-test using an embedded processor
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Journal of Electronic Testing: Theory and Applications
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
Journal of Electronic Testing: Theory and Applications
Enhanced Reduced Pin-Count Test for Full-Scan Design
Journal of Electronic Testing: Theory and Applications
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Reusing Scan Chains for Test Pattern Decompression
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Journal of Electronic Testing: Theory and Applications
Boundary Scan: The Internet of Test
IEEE Design & Test
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Benefits of a SoC-Specific Test Methodology
IEEE Design & Test
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Framework to evaluate Test Tradeoffs in Embedded Core Based Systems-Case Study on TT's TMS320C27xx
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test and Debug Strategy of the PNX8525 Nexperia" Digital Video Platform System Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Space and Time Compaction Schemes for Embedded Cores
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Enhanced Reduced Pin-Count Test for Full-Scan Design
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ATPG for Path Delay Faults without Path Enumeration
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
Quality of Electronic Design: From Architectural Level to Test Coverage
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check
Journal of Electronic Testing: Theory and Applications
Practical Scan Test Generation and Application for Embedded FIFOs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
DFT, Test Lifecycles and the Product Lifecycle
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Trends in SLI design and their effect on test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Features of a Core-Based Co-Processor Array for Video Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
Pattern-based verification of connections to intellectual property cores
Integration, the VLSI Journal
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
Design of reconfigurable access wrappers for embedded core based SoC test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
IEEE Transactions on Computers
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Partial Core Encryption for Performance-Efficient Test of SOCs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process
IEEE Transactions on Computers
SoC test scheduling using the B-tree based floorplanning technique
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-in-Package Testing: Problems and Solutions
IEEE Design & Test
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
Integration, the VLSI Journal
On the identification of modular test requirements for low cost hierarchical test path construction
Integration, the VLSI Journal
Towards Open Network-on-Chip Benchmarks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A non-intrusive isolation approach for soft cores
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
Analysis of the test data volume reduction benefit of modular SOC testing
Proceedings of the conference on Design, automation and test in Europe
Wrapper and TAM co-optimization for reuse of SoC functional interconnects
Proceedings of the conference on Design, automation and test in Europe
Testing diagnostics of modern microprocessors with the use of functional models
Automation and Remote Control
The efficient TAM design for core-based SOCs testing
WSEAS Transactions on Circuits and Systems
An efficient scheduling algorithm based on multi-frequency tam for SOC testing
WSEAS Transactions on Circuits and Systems
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
IEICE - Transactions on Information and Systems
Test time minimization for hybrid BIST of core-based systems
Journal of Computer Science and Technology
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient SoC test technique by reusing on/off-chip bus bridge
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-Area Wrapper Cell Design for Hierarchical SoC Testing
Journal of Electronic Testing: Theory and Applications
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Fault isolation for nonisolated blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression based on geometric shapes
Computers and Electrical Engineering
An efficient link controller for test access to IP core-based embedded system chips
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
A fast and Effective DFT for test and diagnosis of power switches in SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.02 |
Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design,in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced bya design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of newchallenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overviewof current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA andIEEE P1500 and describe the challenges for future research.