Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Microprocessor based testing for core-based system on chip
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A data flow fault coverage metric for validation of behavioral HDL descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
GARDA: a diagnostic ATPG for large synchronous sequential circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing a System-On-a-Chip with Embedded Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
A fast and low-cost testing technique for core-based system-chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
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In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-a-chip (SoC) environments. The approach advantages are the ability to protect the core IP, the simple test interface (thanks also to the adoption of the P1500 standard), the possibility to run the test at-speed, the reduced test time, and the good diagnostic capabilities. The paper reports figures about the achieved fault coverage, the required area overhead, and the performance slowdown, and compares the figures with those for alternative approaches, such as those based on full scan and sequential ATPG.