Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Diagnostic Fault Simulation of Sequential Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Sequential Circuit Diagnosis Based on Formal Verification Techniques
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Fault Distinguishing Pattern Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnostic Test Generation for Sequential Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The paper deals with automated generation of diagnostic test sequences for synchronous sequential circuits. An algorithm is proposed, named GARDA, which is suitable to produce good results with acceptable CPU time and memory requirements even for the largest benchmark circuits. The algorithm is based on Genetic Algorithms, and experimental results are provided which demonstrate the effectiveness of the approach.