Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A fast and memory-efficient diagnostic fault simulation for sequential circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Software accelerated functional fault simulation for data-path architectures
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Symbolic fault simulation for sequential circuits and the multiple observation time test strategy
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fault emulation: a new approach to fault grading
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hybrid Fault Simulation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
On Non-Statistical Techniques for Fast Fault Coverage Estimation
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe
Cellular automata as a built in self test structure
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
GARDA: a diagnostic ATPG for large synchronous sequential circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Low Cost Concurrent Test Implementation for Linear Digital Systems
ETW '00 Proceedings of the IEEE European Test Workshop
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
The Effects of Test Compaction on Fault Diagnosis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computers
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Theory and application of cellular automata for pattern classification
Fundamenta Informaticae - Special issue on cellular automata
Virtual Compression through Test Vector Stitching for Scan Based Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design space exploration for aggressive test cost reduction in CircularScan architectures
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Journal of Integrated Design & Process Science
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simulated fault injections and their acceleration in SystemC
Microprocessors & Microsystems
Reducing fault dictionary size for million-gate large circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scan power reduction in linear test data compression scheme
Proceedings of the 2009 International Conference on Computer-Aided Design
Serial diagnostic fault simulation for synchronous sequential circuits
Integration, the VLSI Journal
Customizing pattern set for test power reduction via improved X-identification and reordering
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Enhancing testability in architectural design for the new generation of core-based embedded systems
HASE'04 Proceedings of the Eighth IEEE international conference on High assurance systems engineering
An automatic test pattern generator for large sequential circuits based on genetic algorithms
ITC'94 Proceedings of the 1994 international conference on Test
A study of IDDQ subset selection algorithms for bridging faults
ITC'94 Proceedings of the 1994 international conference on Test
A hybrid fault simulator for synchronous sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic test pattern generation with BOA
PPSN'06 Proceedings of the 9th international conference on Parallel Problem Solving from Nature
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Theory and Application of Cellular Automata For Pattern Classification
Fundamenta Informaticae - Cellular Automata
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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