Linear Dependencies in Linear Feedback Shift Registers
IEEE Transactions on Computers
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
IEEE Transactions on Computers - Special issue on fault-tolerant computing
On Linear Dependencies in Subspaces of LFSR-Generated Sequences
IEEE Transactions on Computers
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets
ATS '99 Proceedings of the 8th Asian Test Symposium
Test sequence compaction by reduced scan shift and retiming
ATS '95 Proceedings of the 4th Asian Test Symposium
Test Compaction in a Parallel Access Scan Environment
ATS '97 Proceedings of the 6th Asian Test Symposium
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
ATS '98 Proceedings of the 7th Asian Test Symposium
PASTA: Partial Scan to Enhance Test Compaction
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
OPMISR: The Foundation for Compressed ATPG Vectors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing
IEEE Design & Test
On test data volume reduction for multiple scan chain designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
An Arithmetic Structure for Test Data Horizontal Compression
Proceedings of the conference on Design, automation and test in Europe - Volume 1
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
Fast and energy-frugal deterministic test through efficient compression and compaction techniques
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Test data compression technique using selective don't-care identification
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Virtual Compression through Test Vector Stitching for Scan Based Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Data Compression: The System Integrator's Perspective
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Journal of Electronic Testing: Theory and Applications
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Huffman-based coding with efficient test application
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Test response compactor with programmable selector
Proceedings of the 43rd annual Design Automation Conference
On test data compression using selective don't-care identification
Journal of Computer Science and Technology
Scan-BIST based on cluster analysis and the encoding of repeating sequences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GECOM: test data compression combined with all unknown response masking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Low cost scan test by test correlation utilization
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
A Test Data Compression Scheme for Reducing Power Based on OLELC and NBET
ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Theoretical and Methodological Issues
A Variable-Length Coding Adjustable for Compressed Test Application
IEICE - Transactions on Information and Systems
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Scan cell positioning for boosting the compression of fan-out networks
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
Proceedings of the International Conference on Computer-Aided Design
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A test pattern compression scheme is proposed in order to reduce test data volume and application time. The number of scan chains that can be supported by an ATE is significantly increased by utilizing an on-chip decompressor. The functionality of the ATE is kept intact by moving the decompression task to the circuit under test. While the number of virtual scan chains visible to the ATE is kept small, the number of internal scan chains driven by the decompressed pattern sequence can be sinificantly increased.