Nine-coded compression technique for testing embedded cores in socs

Authors:
Mohammad Tehranipoor;Mehrdad Nourani;Krishnendu Chakrabarty
Affiliations:
Department of Computer Science and Electrical Engineering, University of Maryland Baltimore County, Baltimore, MD;Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX;Department of Electrical and Computer Engineering, Duke University, Durham, NC
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed- and variable-length blocks. In spite of its simplicity, it provides significant reduction in testdata volume and test-application time. The decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Our technique is flexible and can be efficiently adopted for single- or multiple-scan chain designs. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.