Test data compression using four-coded and sparse storage for testing embedded core

Authors:
Zhang Ling;Kuang Ji-shun;You zhi-qiang
Affiliations:
College of Computer and Communication, Hunan University, Changsha, China;College of Computer and Communication, Hunan University, Changsha, China;School of software, Hunan University, Changsha, China
Venue:
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
Year:
2010

Citing 12
Cited 1

Test set compaction algorithms for combinational circuits

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A case study on the implementation of the Illinois Scan Architecture

Proceedings of the IEEE International Test Conference 2001
BIST-Aided Scan Test - A New Method for Test Cost Reduction

VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression

VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Technique for High Ratio LZW Compression

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RL-huffman encoding for test compression and power reduction in scan applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

IEEE Design & Test
Nine-coded compression technique for testing embedded cores in socs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedded deterministic test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Test Data Compression Using Selective Sparse Storage

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

this paper presents a new test-data compression technique that uses exactly four codewords and sparse storage for testing embedded cores. It provides significant reduction in test-data volume with no any complex algorithm. It aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. In addition, the decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.