CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Design space exploration for aggressive test cost reduction in CircularScan architectures
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
IEICE - Transactions on Information and Systems
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using four-coded and sparse storage for testing embedded core
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
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It is common to use ATPG of scan-based design forhigh fault coverage in LSI testing. However, significantincrease in test cost is caused in accordance withincreasing design complexity. Recent strategies for testcost reduction combine ATPG and BIST techniques.Unfortunately, these strategies have serious constraints.We propose a new method that employs ATE and BISTstructures to apply coded test patterns to LSI circuits.Results obtained using practical circuits show drastic testcost reduction capability of the proposed method.