Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
BIST-Aided Scan Test - A New Method for Test Cost Reduction
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs
Proceedings of the conference on Design, automation and test in Europe
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In this paper, we propose a scheme for test data reduction which uses broadcaster along with bit-flipping circuit. The proposed scheme can reduce test data without degrading the fault coverage of ATPG, and without requiring or modifying the arrangement of CUT. We theoretically analyze the test data size by the proposed scheme. The numerical examples obtained by the analysis and experimental results show that our scheme can effectively reduce test data if the care-bit rate is not so much low according to the number of scan chains. We also discuss the hybrid scheme of random-pattern-based flipping and single-input-based flipping.